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SSM9975M/GM
DUAL N-CHANNEL ENHANCEMENT-MODE POWER MOSFETS
Simple drive requirement Lower gate charge Fast switching characteristics
D2 D1 D1
D2
BV DSS R DS(ON)
G2 S2
60V 21m 7.6A
ID
SO-8
S1
G1
Description
D1 D2
Advanced Power MOSFETs from Silicon Standard provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The SSM9975M is in the SO-8 package, which is widely preferred for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters.
G1 S1
G2 S2
This device is available with Pb-free lead finish (second-level interconnect) as SSM9975GM.
Absolute Maximum Ratings
Symbol VDS VGS ID @ TA=25C ID @ TA=100C IDM PD @ TA=25C TSTG TJ Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Continuous Drain Current Pulsed Drain Current
1 3 3
Rating 60 25 7.6 6.1 30 2 0.016 -55 to 150 -55 to 150
Units V V A A A W W/C C C
Total Power Dissipation Linear Derating Factor Storage Temperature Range Operating Junction Temperature Range
Thermal Data
Symbol Rthj-a Parameter Thermal Resistance Junction-ambient
3
Value Max. 62.5
Unit C/W
12/10/2004 Rev.2.01
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SSM9975M/GM
Electrical Characteristics @ Tj=25oC (unless otherwise specified)
Symbol BVDSS Parameter Drain-Source Breakdown Voltage Static Drain-Source On-Resistance2 Gate Threshold Voltage Forward Transconductance
Drain-Source Leakage Current (Tj=25 C) Drain-Source Leakage Current (Tj=70 C)
o o
Test Conditions VGS=0V, ID=250uA VGS=10V, ID=7A VGS=4.5V, ID=5A VDS=VGS, ID=250uA VDS=10V, ID=7A VDS=60V, VGS=0V VDS=48V ,VGS=0V VGS= 25V ID=7A VDS=48V VGS=4.5V VDS=30V ID=1A RG=3.3 , VGS=10V RD=30 VGS=0V VDS=25V f=1.0MHz f=1.0MHz
Min. 60 1 -
Typ. 0.06 12 26 6 14 14 7 40 13 200 170 0.86
Max. Units 21 27 3 1 25 100 40 V V/C m m V S uA uA nA nC nC nC ns ns ns ns pF pF pF
BV DSS/ Tj
RDS(ON) VGS(th) gfs IDSS IGSS Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Rg
Breakdown Voltage Temperature Coefficient Reference to 25C, ID=1mA
Gate-Source Leakage Total Gate Charge
2
Gate-Source Charge Gate-Drain ("Miller") Charge Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance
2
2320 3700
Source-Drain Diode
Symbol VSD Parameter Forward On Voltage
2 2
Test Conditions IS=1.7A, VGS=0V IS=7A, VGS=0V, dI/dt=100A/s
Min. -
Typ. 34 48
Max. Units 1.2 V ns nC
trr
Qrr
Reverse Recovery Time
Reverse Recovery Charge
Notes:
1.Pulse width limited by max. junction temperature. 2.Pulse width <300us , duty cycle <2%. 3.Surface mounted on 1 in2 copper pad of FR4 board ; 135C/W when mounted on min. copper pad.
12/10/2004 Rev.2.01
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SSM9975M/GM
130
100
117
T A = 25 C
o
10V 7.0V
80
TA=150 C
o
10V 7.0V
104
ID , Drain Current (A)
ID , Drain Current (A)
91
78
5.0V 4.5V
60
5.0V 4.5V
65
52
40
39
V G =3.0V
20
26
V G =3.0V
13
0 0 2 4 6 8 10 12
0 0 2 4 6 8 10 12
V DS , Drain-to-Source Voltage (V)
V DS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
27
2.5
ID=5A T A =25 o C
25 2.0
ID=7A V G =10V
Normalized RDS(ON)
RDS(ON) (m )
1.5
23
1.0
21 0.5
19
3 5 7 9 11
0.0 -50 0 50 100 150
V GS , Gate-to-Source Voltage (V)
T j , Junction Temperature ( C)
o
Fig 3. On-Resistance vs. Gate Voltage
Fig 4. Normalized On-Resistance vs. Junction Temperature
2.5
7
6
2
5
4
VGS(th) (V)
IS(A)
3
T j =150 o C
T j =25 o C
1.5
2
1
1
0 0 0.2 0.4 0.6 0.8 1 1.2
0.5
-50
0
50
100
150
V SD , Source-to-Drain Voltage (V)
T j ,Junction Temperature ( C)
o
Fig 5. Forward Characteristic of Reverse Diode
Fig 6. Gate Threshold Voltage vs. Junction Temperature
12/10/2004 Rev.2.01
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SSM9975M/GM
f=1.0MHz
14 10000
ID=7A
12
VGS , Gate to Source Voltage (V)
10
V DS =48V V DS =38V V DS =30V C (pF)
1000
C iss
8
6
4
2
C oss C rss
100 0 10 20 30 40 50 60 1 5 9 13 17 21 25 29
0
Q G , Total Gate Charge (nC)
V DS , Drain-to-Source Voltage (V)
Fig 7. Gate Charge Characteristics
Fig 8. Typical Capacitance Characteristics
100
1
Duty factor=0.5
Normalized Thermal Response (R thja)
0.2
10
1ms ID (A)
1
0.1
0.1
0.05
10ms 100ms
PDM
0.02
t T
Duty factor = t/T Peak Tj = PDM x Rthja + Ta
0.01
0.01
0.1
T A =25 C Single Pulse
0.01 0.1 1 10
o
1s
Single Pulse
Rthja = 135C/W
DC
100 1000
0.001 0.0001 0.001 0.01 0.1 1 10 100 1000
V DS , Drain-to-Source Voltage (V)
t , Pulse Width (s)
Fig 9. Maximum Safe Operating Area
Fig 10. Effective Transient Thermal Impedance
VDS 90%
VG QG 4.5V QGS QGD
10% VGS td(on) tr td(off) tf Charge Q
Fig 11. Switching Time Waveform
12/10/2004 Rev.2.01
Fig 12. Gate Charge Waveform
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SSM9975M/GM
Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties.
12/10/2004 Rev.2.01
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